A1.1 · Book pp. 2–23
Computer hardware and operation
What actually happens between you pressing a key and something appearing on the screen? This section follows an instruction through the hardware that runs it.
What you need to know
Parts marked HL are for Higher Level only. Switch to SL at the top and they disappear.
| Point | Topic | Level |
|---|---|---|
| A1.1.1 | The main parts of the CPU and how they work together | SL + HL |
| A1.1.2 | The role of the GPU | SL + HL |
| A1.1.3 | The difference between the CPU and the GPU | HL |
| A1.1.4 | Why there are different types of primary memory | SL + HL |
| A1.1.5 | The fetch, decode and execute cycle | SL + HL |
| A1.1.6 | Pipelining in multi-core architectures | HL |
| A1.1.7 | Internal and external secondary storage | SL + HL |
| A1.1.8 | Compression | SL + HL |
| A1.1.9 | Cloud service types | SL + HL |
🔬 Try this first
Run a free benchmark on your own computer, then find your CPU’s core count, RAM and storage type. Keep the numbers next to you and connect each one to a topic as you work through this section.
A1.1.1 Inside the CPU
The central processing unit does most of the processing in a device. Three groups of parts work together:
Registers
| Register | What it holds |
|---|---|
| PC program counter | The address of the next instruction |
| MAR memory address register | The address being read or written now |
| MDR memory data register | The data just fetched, or about to be written |
| IR instruction register | The instruction being executed |
| AC accumulator | Intermediate results from the ALU |
Buses
| Bus | Carries | Direction | Why width matters |
|---|---|---|---|
| Address | Which location to use | One way, from the CPU | Sets how much memory can be addressed: n lines give 2n locations |
| Data | The data itself | Both ways | Sets how much moves at once: commonly 8, 16, 32 or 64 bits |
| Control | Read/write, interrupts, clock and status signals | Both ways | It carries signals, so its lines are named for jobs |
Cores
| Type | How it works | Good for |
|---|---|---|
| Single-core | One processing unit shared between tasks | Simple, low-cost devices |
| Multi-core | Two or more cores run instructions at the same time | Multitasking, gaming, servers |
| Co-processor | A specialist chip takes work from the CPU | Graphics, audio, signal processing |
⚠️ Common mistake
Four cores do not mean four times the speed. Software must be written to use several cores, and memory speed still limits the whole system.
Check yourself
- How do the MAR and PC work together? The PC’s value is copied to the MAR, and the MAR puts it on the address bus.
- What does doubling the data bus width change? Twice as many bits move in each transfer.
- What does adding one line to the address bus change? It doubles the addressable locations.
A1.1.2 The role of the GPU
A graphics processing unit speeds up work by doing a huge number of simple calculations at the same time. This is called parallel processing. It was built for graphics, and its structure turned out to suit other kinds of work too.
| Use | Why a GPU helps |
|---|---|
| Video games | Applies shaders and textures across a whole scene for every frame |
| Video | Speeds up decoding and encoding, especially at 4K and above |
| AI and machine learning | Models rely on matrix and vector multiplication, which runs well in parallel |
| Cryptocurrency mining | Repeats hashing attempts very quickly, though ASICs have replaced GPUs in many operations |
HL A1.1.3 CPU compared with GPU
| CPU | GPU | |
|---|---|---|
| Purpose | General purpose: many kinds of task | Specialized: large amounts of data in parallel |
| Cores | A few powerful cores, commonly 4–8 in user devices | Hundreds to thousands of small cores |
| Strength | Quick decisions, branch prediction, out-of-order execution | The same operation on many data points |
| Memory | Small, fast caches for small repeated reads | VRAM with high bandwidth for large blocks |
| Power | Lower for general work | Higher under heavy parallel load |
| Typical work | OS, applications, game logic | Rendering, video, deep learning |
One frame of a game
- Input: you press a key, and the CPU works out the new position using the game’s rules and physics.
- Prepare: the CPU sends the updated state to the GPU.
- Render: the GPU draws the frame, with lighting, shading and textures.
- Display: the frame reaches the screen and the loop starts again.
Check yourself
- Why did GPUs spread into AI? Training involves huge numbers of simple matrix calculations that can run at the same time.
- What are shaders and textures? Techniques that add lighting, effects and surface detail to 3D models.
A1.1.4 Primary memory
Primary memory is memory the CPU uses directly. Each type exists because no single memory can be fast, large, cheap and permanent all at once.
| Type | Volatile? | Purpose |
|---|---|---|
| Registers | Yes | Data the CPU is working on this instant |
| Cache L1 (32–128 KB per core) | Yes | Fastest cache, usually split into instructions and data |
| Cache L2 (256 KB–2 MB per core) | Yes | Larger and slightly slower than L1 |
| Cache L3 (2–64 MB shared) | Yes | Largest and slowest cache, often shared by all cores |
| RAM | Yes | Programs and data currently in use |
| ROM | No | Start-up firmware such as the BIOS, which tests hardware and loads the OS |
The CPU looks in cache first, then RAM, then secondary storage. Finding the data in cache is a cache hit. Not finding it is a cache miss, and the CPU has to wait for slower memory.
Check yourself
- Why does a larger cache usually help? It holds more data, so there are more hits.
- What is prefetching? Predicting what data is needed soon and loading it into cache ahead of time.
- Why is your phone’s app switcher fast? Recent apps stay in RAM, so they do not reload from storage.
A1.1.5 Fetch, decode, execute
Every instruction a CPU runs goes through the same three stages:
- Fetch: the instruction at the address in the PC is copied from memory into the IR. The PC moves on.
- Decode: the control unit works out what the instruction means.
- Execute: the CPU carries it out, which might use the ALU, memory or a device.
The Little Man Computer (LMC) is a teaching model of a CPU. Each instruction is a three-digit code, so you can watch the registers change at every stage.
| Mnemonic | Code | Meaning |
|---|---|---|
| INP | 901 | Input a value into the accumulator |
| OUT | 902 | Output the accumulator |
| LDA | 5xx | Load from address xx into the accumulator |
| STA | 3xx | Store the accumulator at address xx |
| ADD | 1xx | Add the value at xx to the accumulator |
| SUB | 2xx | Subtract the value at xx from the accumulator |
| BRA | 6xx | Always branch to xx |
| BRZ | 7xx | Branch to xx if the accumulator is zero |
| BRP | 8xx | Branch to xx if the accumulator is zero or positive |
| HLT | 000 | Stop |
| DAT | none | Reserve a mailbox and set its value |
✍️ Write your own
Type each program into the lab and test it. The dropdown has model answers for 1, 3 and 4.
- Input two numbers, add them and output the result.
- Input a number and output 1 if it is zero, or 0 if it is not.
- Add 1 + 2 + 3 + 4 + 5 using a loop and output the total.
- Input two numbers and output the larger.
- Stretch: input three numbers and output them in ascending order.
⚠️ Common mistake
The PC does not wait for execute. It moves on during the fetch, so it already points at the next instruction before decoding starts. Branch instructions then overwrite it during execute.
HL A1.1.6 Pipelining
Picture a noodle stall with four stations. If each customer must finish all four before the next can start, three stations stand idle at any moment. If the next customer steps in as soon as the first station is free, every station stays busy. That is pipelining: instructions overlap, each at a different stage.
A classic pipeline has five stages: fetch, decode, execute, memory access, write back. Results pass between stages through interface registers, also called latches or buffers, and one clock keeps every stage in step.
Pipelines and multiple cores
| Idea | Meaning | At the noodle stall |
|---|---|---|
| Independent execution | Each core runs its own pipeline without waiting for the others | Two stalls serve different customers |
| Parallel execution | Cores work on different parts of one large task | Stalls split one huge catering order |
✏️ Book note
The syllabus title says “in multi-core architectures”, but a single core can be pipelined too. Each core has its own pipeline, and a multi-core chip adds parallelism on top.
Check yourself
- Which bus carries the address in a fetch? The address bus, with a read signal on the control bus and the instruction returning on the data bus.
- Why must registers and memory work together in a fetch? Instructions live in memory, but the CPU can only act on them once they are in its registers.
A1.1.7 Secondary storage
Secondary storage keeps data with the power off. Choosing one is a trade-off between speed, capacity, cost and portability.
Internal
| HDD | SSD | |
|---|---|---|
| Technology | Spinning magnetic disks with moving heads | Flash memory, no moving parts |
| Speed | About 50–150 MB/s | About 200–500 MB/s on SATA, faster on NVMe |
| Durability | Easily damaged by knocks | Resists shock |
| Noise, power, heat | More of each | Silent, with less power and heat |
| Cost per GB | Lower | Higher |
| Best for | Large backups, media archives | OS, apps, games, laptops |
M.2 SSDs are small sticks that slot into the motherboard. eMMC is flash storage soldered to the board in low-cost phones and laptops: slower than an SSD, but enough for basic use.
External
| Type | Strength | Weakness |
|---|---|---|
| External HDD | Large capacity for the price | Slower, sensitive to knocks |
| External SSD | Fast and portable | Costs more per GB |
| Optical disc | Cheap for archiving and playback | Scratches easily, needs a drive that few devices now have |
| Memory card | Tiny and tough, suits cameras and phones | Slower than an SSD |
| NAS | Shared by a network, expandable, often uses RAID | Needs a network and more setup |
Check yourself
- Why might a cheap phone use eMMC? It is cheaper and meets basic needs.
- What does a NAS add for a business? One central place to store, share and back up files.
- Memory card or optical disc for a hiking camera? A memory card: small, tough and rewritable.
A1.1.8 Compression
Compression stores information in fewer bits, so files take less space and move faster across a network.
| Lossless | Lossy | |
|---|---|---|
| Can the original be restored? | Yes, exactly | No, data is removed for good |
| How it works | Removes statistical redundancy | Removes detail people notice least |
| File size | Larger | Usually much smaller |
| Used for | Text, databases, code | Images, audio, video |
Run-length encoding (lossless)
RLE replaces each run of repeated characters with a count and the character. It is excellent for data with long runs and poor for data without them, and it can even make a file bigger.
Transform coding (lossy)
JPEG and MP3 both use transform coding. For a JPEG:
- Split the image into small square blocks.
- Transform each block with the discrete cosine transform (DCT), which turns pixel values into low- and high-frequency coefficients.
- Quantize: reduce the precision of the high-frequency coefficients. Eyes notice this fine detail least. This is the step that loses data.
- Encode the result with a zigzag scan, then RLE, then Huffman coding.
✍️ Programming exercise
Write a program with two options: compress a string with RLE, or decompress one. Try it before opening the answer.
Python model answer
def compress(text):
if not text:
return ""
result, count = "", 1
for i in range(1, len(text)):
if text[i] == text[i - 1]:
count += 1
else:
result += str(count) + text[i - 1]
count = 1
return result + str(count) + text[-1]
def decompress(code):
result, digits = "", ""
for ch in code:
if ch.isdigit():
digits += ch
else:
result += ch * int(digits)
digits = ""
return result
print(compress("MMMMMOOPPPPPPPQ")) # 5M2O7P1Q
print(decompress("5M2O7P1Q")) # MMMMMOOPPPPPPPQ Check yourself
- Why does RLE work well on a fax page? Most of the page is long runs of white.
- Why is RLE poor for a portrait photo? Neighbouring pixels rarely match exactly, so runs are short.
- Which step makes JPEG lossy? Quantization, because the discarded precision cannot be restored.
A1.1.9 Cloud service types
The three models differ in how much you manage yourself and how much the provider manages for you.
| SaaS | PaaS | IaaS | |
|---|---|---|---|
| You get | A finished application | A platform to build and deploy on | Virtual machines, storage, networks |
| You manage | Your data and settings | Your app and data | OS, apps, data and their security |
| Used by | End users | Developers | IT teams |
| Upside | No install, automatic updates, use on any device | Focus on code, scales easily | Most control, no hardware to buy |
| Downside | Needs internet, relies on provider’s security | Vendor lock-in, less control | Needs the most technical skill |
| Example | Google Workspace | Azure App Service | AWS EC2 |
✏️ Book correction
A heading in the book expands SaaS as “Software as a Solution”. The correct term is Software as a Service, which the book uses everywhere else.
Check yourself
- How does SaaS differ from installed software? It runs on the provider’s servers and is reached over the internet.
- Why pick IaaS over buying hardware? Low upfront cost and resources that scale with demand.
Quick quiz
HL Extra questions
Exam-style questions
These are written for this site in the style of Paper 1. Answer on paper first, then open the mark points.
-
Describe the function of the control unit. [2]
Mark points
- Directs the fetch, decode and execute of instructions [1].
- Sends control signals to coordinate memory, the ALU and I/O devices [1].
-
Outline why the memory address register is needed during a fetch. [2]
Mark points
- It holds the address of the location being accessed [1].
- It places that address on the address bus so memory can return the contents [1].
-
A video-editing workstation has a choice of a dual-core or an eight-core CPU at the same clock speed. Explain one reason the eight-core CPU may not run an older program faster. [3]
Mark points
- The program may have been written to use a single thread [1].
- It can only run on one core at a time [1].
- So the extra cores stay idle for that program and its speed does not change [1].
-
Explain why a computer has cache memory as well as RAM. [3]
Mark points
- RAM is much slower than the CPU [1].
- Cache keeps frequently used data and instructions close to the CPU [1].
- More requests are cache hits, so the CPU spends less time waiting [1].
-
Describe the role of the buses during the fetch stage. [4]
Mark points
- The address in the MAR is placed on the address bus [1].
- The control bus carries a read signal [1].
- Memory places the instruction on the data bus [1].
- The instruction arrives in the MDR and is copied to the IR [1].
-
A school keeps 400 TB of old CCTV footage that is rarely viewed. Suggest whether it should use HDDs or SSDs, and justify your choice. [3]
Mark points
- HDDs [1].
- They cost less per GB, which matters at this volume [1].
- Read speed matters little because the footage is rarely viewed [1].
-
Distinguish between lossless and lossy compression, giving a suitable use of each. [4]
Mark points
- Lossless restores the original exactly [1]; for example, a source code or text file [1].
- Lossy permanently removes data that people are less likely to notice [1]; for example, a JPEG photo or streamed audio [1].
-
A start-up is choosing IaaS rather than buying servers. Outline one advantage and one disadvantage, and state one thing it remains responsible for. [3]
Mark points
- Advantage: low upfront cost, or it can scale up as users grow [1].
- Disadvantage: it needs the technical skill to run the systems [1].
- Responsible for: its operating systems, applications or data security [1].
HL Exam-style questions
-
Compare how a CPU and a GPU are designed, and link each design to a task it suits. [4]
Mark points
- CPU: a few powerful, general-purpose cores [1], which suit varied work and quick decisions such as running the OS [1].
- GPU: thousands of smaller cores working in parallel [1], which suit repeating one operation on lots of data, such as rendering a frame [1].
-
Explain how a CPU and GPU cooperate in one frame of a video game. [3]
Mark points
- The CPU processes player input and updates the game state [1].
- It sends the new positions and scene data to the GPU [1].
- The GPU renders the frame with lighting and textures for the display [1].
-
A processor has five pipeline stages, each taking one cycle. Calculate the cycles needed for 6 instructions with and without pipelining, then explain the difference. [4]
Mark points
- Without: 6 × 5 = 30 cycles [1].
- With: 5 + 6 − 1 = 10 cycles [1].
- Without pipelining, one instruction must finish before the next starts [1].
- With pipelining, a new instruction enters as soon as the first stage is free, so instructions overlap [1].